The present invention relates to a semiconductor memory device and to a method for manufacturing capacitors in a semiconductor memory device.
With increasing integration in a dynamic random access memory (DRAM), a memory cell region for storing 1 bit, which is a unit of storage in the memory device, becomes decreased. Meanwhile, an area of a capacitor may not decrease as much as that of the unit cells. This is because a capacitance charge per cell is needed to prevent soft error and to maintain an operational safety margin. Therefore, there are three methods for maintaining proper memory capacitance within a limited cell region. The first method reduces the thickness of a dielectric. The second method makes a capacitor bottom electrify with a three-dimensional structure with a large effective area. The third method uses high dielectric constant materials.
A dielectric layer capacitor has a high dielectric constant material such as TiO2, Ta2O5, ZrO2, (BaSr)TiO3 (BST), (PbZr)TiO3 (PZT), (PbLa) (ZrTi)O3 (PLZT), (PbLa)TiO3 (PLT), TaON, etc. Among the above-mentioned materials, the barium strontium titanate (BST) layer is expected to be a preferred high dielectric layer, which is adapted to 0.10 xcexcm technology. The BST dielectric layer has a high dielectric constant of about 200 to 400, and it is crystallized on a metal layer, so it has a metal-insulator-metal (MIM) structure. The metal layer, which is used as an electrode, can be any material selected from Pr, Ir, Ru, RuO2 or IrO2.
However, the BST layer itself is unstable, and therefore makes an etching process of a metal electrode so difficult as to cause many problems in the integration process, like deterioration caused by hydrogen. When a capacitor electrode is formed with a metal layer including a platinum layer, a barrier layer is necessarily formed. The barrier layer prevents reaction with a polysilicon plug, and prevents diffusion of oxygen, which is used as a source in depositing a dielectric layer and annealing the dielectric layer.
Also, in a stacked capacitor having three-dimensional structure corresponding to a highly integrated DRAM, producing a higher bottom electrode renders more difficult an etching process of the bottom electrode. Therefore, the conventional art utilizes a concave capacitor to avoid the difficulties associated with the etching process. According to the conventional method for manufacturing the concave capacitor, an interlayer insulating layer is formed on a portion where a bottom electrode is formed, and a storage node hole is formed within the interlayer insulating layer. After that, a platinum metal layer, which is a bottom electrode, is deposited at a predetermined thickness to form a storage electrode.
When forming the concave capacitor mentioned above, a platinum metal etching process is easily performed, and the height of a storage node may be regulated to prevent misalignment between a storage node contact and the storage node.
Also, higher integration of a concave capacitor results in increasing the height of an oxide, which is used as an interlayer insulating layer for assuring a region. As a result, dielectric materials may be formed in a deep valley of a storage node. That is, when depositing the BST layer using chemical vapor deposition (CVD) to obtain a large step coverage, the reliability of an electric characteristic of the BST layer between a surface and the valley is not guaranteed.
FIG. 1 is a cross-sectional view of a conventional concave capacitor. A first interlayer insulating layer 205 is deposited on a semiconductor substrate 200 to form a contact hole, and a plug 210 is formed by filling the contact hole with a conducting layer. After that, a second interlayer insulating layer 215 is deposited to form a concave capacitor and a storage node hole is formed. A bottom electrode 220, a CVD-BST layer 225 and a top electrode 230 are consecutively formed on the storage node hole thereon. In FIG. 1, in the regions of A, B, C, D and E, electric characteristics are unstable and produce a high leakage current, etc., due to the composition difference between Ba+Sr and Ti in CVD-BST process. This problem is generated when a gas phase reaction in the CVD deposition process causes unstable surface reactions according to the topology. Since the BST capacitor has sensitive electric characteristics, the above-mentioned problem as a large effect on the reliability of the whole device.
It is, therefore, an object of the present invention to provide a method for manufacturing a memory device having a BST capacitor in a concave structure by using the atomic layer deposition (ALD) capable of providing a good step-coverage of a dielectric material therein and by using the chemical vapor deposition (CVD) method in forming other thick layers required to form the BST capacitor.
The invention, in part, pertains to a method for manufacturing a memory device having a dielectric layer, which includes forming a seed layer as a first dielectric layer by using a ALD method, and forming a second dielectric layer by using a CVD method. The first dielectric layer can be an ALD-BST layer, and the second dielectric layer can be a CVD-BST layer.
The invention, in part, pertains to a method for manufacturing a memory device which includes the steps of: forming a first interlayer insulating layer having a contact hole on a semiconductor substrate, forming a contact plug that is connected to the semiconductor substrate, forming a second interlayer insulating layer on the first interlayer insulating layer and the contact plug, forming a storage node hole by applying a selective etching process to the second interlayer insulating layer, thereby exposing the contact plug, forming a bottom electrode pattern on the exposed contact plug, successively forming an ALD-BST layer and a CVD-BST layer on the bottom electrode to form a dielectric layer, and depositing a top electrode on the dielectric layer. The first interlayer insulating layer includes oxide and nitride layers, and the nitride layer forms at a thickness of about 300 xc3x85 to about 1000 xc3x85.
The invention, in part, pertains to the step of forming the contact plug, in which includes the steps of forming a contact hole by applying a selective etching process to the first interlayer insulating layer, filling the contact hole with a polysilicon layer and applying an etch back process to the polysilicon layer to form a recess, and filling the recess with a silicide or barrier metal layer. The polysilicon layer can be a doped polysilicon layer formed at a thickness of about 500 xc3x85 to about 3000 xc3x85 using chemical vapor deposition. The plug recess has a depth of about 500 xc3x85 to about 1500 xc3x85. Also, the silicide layer is a TiSix layer which is formed by forming a Ti layer on the plug recess at a thickness of about 100 xc3x85 to about 300 xc3x85, applying a thermal treatment to the Ti layer, and removing a non-reaction Ti layer using a wet etching process. In the invention, the barrier metal layer can be any one of TiN, TiSiN, TaAIN and a mixed layer thereof, and the barrier metal layer is deposited by a PVD or CVD method. Also, filling the recess is performed by applying a planarization process to the barrier metal layer by a chemical mechanical polishing method.
The invention, in part, pertains to the second interlayer insulating layer being formed by successively depositing an etching barrier layer, an oxide layer and a reflection barrier layer. The etching barrier layer can be a SiON layer.
The invention, in part, pertains to the step of forming the bottom electrode pattern including forming a conductive layer on the resulting structure including the storage node hole, forming a sacrificial layer on the conductive layer within the storage node hole, removing a portion of the conductive layer and a portion of the sacrificial layer in order to separate the conductive layer into a plurality of bottom electrodes, and removing the remnant of the sacrificial layer. Also, the conductive layer may be any one of Ru, Pt, Ir, Os, W, Mo, Co, Ni, Au or Ag. The conductive layer is deposited by a CVD method and the conductive layer is formed at a thickness of about 50 xc3x85 to about 500 xc3x85 and at a substrate temperature of about 200xc2x0 C. to about 500xc2x0 C.
The invention, in part, pertains to the sacrificial layer being formed with a photoresist layer or an oxide layer. When the sacrificial layer is a photoresist layer, a portion of the sacrificial layer is removed by an ashing process after being separated into the bottom electrodes. When the sacrificial layer is an oxide layer, a portion of sacrificial layer is removed by a wet etching process after being separated into the bottom electrodes. Also, the ALD-BST layer is formed at a temperature of about 150xc2x0 C. to about 300xc2x0 C. and at a thickness of about 20 xc3x85 to about 100 xc3x85. In the invention, after depositing the ALD-BST layer, a plasma thermal treatment is performed in an atmosphere comprising at least one of N2O, H2 or O2 for about 30 to about 180 seconds and at a temperature of about 300xc2x0 C. to about 400xc2x0 C., and power is applied in a range of about 100 W to about 1 kW. Further, the CVD-BST layer can be deposited at a substrate temperature of about 400xc2x0 C. to about 600xc2x0 C. and at a thickness of 50 xc3x85 to 200 xc3x85. After depositing the CVD-BST layer, a rapid thermal nitridation (RTN) is performed in an atmosphere of N2 or N2O2 gas, and a thermal treatment is carried out for about 30 to about 180 seconds and at a temperature of about 500xc2x0 C. to about 700xc2x0 C. The top electrode is any of Ru, Pt, Ir, Os, W, Mo, Co, Ni, Au and Ag, and the top electrode is formed by a CVD method.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.